Hardware 3D graphics processors represent pipelines composed of several stages chained together where each stage performs processing of a certain type of graphics elements such as vertices, geometrical primitives and pixels (or fragments) of the final image and outputs of a stage being inputs for a following stage. Evolution of 3D hardware pipeline implementations went from the fixed function, configurable ones to the flexible, programmable ones with different degree of programmability in the various pipeline stages. For example, for certain designs a programmable vertex stage was followed by a completely fixed-function configurable fragment stage, like in PICA200 series of 3D graphics accelerators of Digital Media Professionals, Inc. Being more general in their operations, programmable pipeline stages are less efficient in the terms of performance and gate size compared to the fixed function pipeline implementations, but the benefits of greater flexibility for programmable pipelines eventually eliminated fixed-function implementations from the space of desktop 3D graphics processors. Meanwhile, embedded space applications still enforce limitations in available gate size and power consumption, thus causing most of the commercial 3D HW implementations in embedded space to be only partially programmable at best (having heterogeneous design with respect to programmability of vertex/geometry transformation and fragment rasterization parts) or have noticeably reduced performance for the fully programmable designs compared to the fixed-function ones on certain operations. Thus, in embedded space there exists a need for a design that combines performance and low power consumption of the fixed function 3D HW pipelines with flexibility of the programmable ones, and (unlike applications in desktop space) such a need is critical as inability to meet power consumption limitations will most likely prevent 3D HW pipeline implementation from the use in embedded space product.
The specification of U.S. Pat. No. 7,865,894 discloses distributing processing tasks within a processor.
The specification of U.S. Pat. No. 7,852,346 discloses a programmable graphic processor for generalized texturing.
The specification of U.S. Pat. No. 7,623,132 discloses a programmable shader having register forwarding for reduced register file bandwidth consumption.
The specification of U.S. Pat. No. 7,706,633 discloses GPU-based image manipulation method for registration applications.
The specification of U.S. Pat. No. 7,777,748 discloses PC-level computing system with a multi-mode parallel graphic rendering subsystem employing an automatic mode controller, responsive to performance data collected during the run-time of graphic applications.
The specification of U.S. Pat. No. 7,911,480 discloses compression of multiplesample antialiasing tile data in a graphic pipeline
The specification of US2006/0082578 discloses an image processor, image processing method and image processing program product. All of the contents in these references are incorporated herein by reference.